1. Field of the Invention
The field of the present invention relates to electronic design automation and, more particularly, to methods and systems for testing integrated circuits during manufacturing and/or fabrication stages.
2. Background
Circuit chip designers often use electronic design automation (EDA) software tools to assist in the design process, and to allow simulation of a chip design prior to prototyping or production. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. Typically, the chip designer designs a circuit by inputting information at a computer workstation generally having a high quality graphics capability so as to display portions of the circuit design as needed. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog(copyright) or VHDL, for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then xe2x80x9cplacedxe2x80x9d (i.e., given specific coordinate locations in the circuit layout) and xe2x80x9croutedxe2x80x9d (i.e., wired or connected together according to the designer""s circuit definitions). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity. After this specific cell-to-cell connectivity has been established, the physical design and layout software creates a physical layout file of the integrated circuit, including the physical position of each metal line (i.e., wire) and each via (i.e., metal transition between chip layers).
As a last step before creation of the mask file for delivery to the fabrication facility, the physical verification and layout validation software performs several design rule checks (DRCs) on the layout file. More recently, in order to handle very large and complex designs, a netlist is created for each section or block in the design. The subsequently placed and routed blocks are then hierarchically viewed as xe2x80x9ccellsxe2x80x9d at the next, full design level, and again placed and routed to form the layout of the whole chip. In this hierarchical approach, the DRCs are also performed hierarchically. Further explanation of a particular chip design process is set forth, for example, in U.S. Pat. No. 5,838,583, hereby incorporated by reference as if fully set forth herein.
During fabrication at a semiconductor foundry, integrated circuits are typically manufactured on semiconductor wafers as part of a multi-step process. A single integrated circuit design is generally duplicated numerous times over a single semiconductor wafer, with iterations of the integrated circuit laid out evenly in rows and columns on the semiconductor wafer. Fabrication of a semiconductor wafer containing integrated circuits may involve etching, deposition, diffusion, and cleaning processes, all carried out within specified tolerances.
Typically, some of the integrated circuits on the semiconductor wafer will not be suitable for commercial use due to imperfections in the manufacturing process. The number of integrated circuits on each wafer that will be problematic depends in part on the quality and consistency of the fabrication process. However, despite the often best efforts of semiconductor foundries, there will usually be a number of integrated circuits on each wafer that need to be rejected, even though the design xe2x80x9cblueprintxe2x80x9d is correct, because during the fabrication process electrical components do not meet the proper tolerances, because electrical connections that should be made are not sufficiently conductive, because electrical paths that should be isolated become too close together or shorted, or because of other imperfections that may occur at any point in the etching, deposition, diffusion or cleaning processes. The endless push to decrease the size of integrated circuits, including the micro-circuitry, wires and components forming a part thereof, merely increases the likelihood that imperfections will occur during the fabrication process requiring rejection of at least some (and sometimes all) of the integrated circuits on a semiconductor wafer.
After the fabrication process, a semiconductor wafer typically goes through a packaging process in which the wafer is diced into dies and then packaged for shipment or integration in electronic devices. The failure to identify problematic integrated circuits before such shipment or integration can be devastating. If an imperfect integrated circuit is not identified before shipping, it may be placed in a product and sold to a consumer or end user, whereupon it will eventually fail during operation. Besides hurting the reputation of the chip designer and semiconductor fabrication facility, such operational failures can also cause major problems to the application of the consumer or end user. Furthermore, the cost of replacing the whole defective product is much greater than removing the defective component from the manufacturing process before it is assembled into the final product.
Consequently, integrated circuits should to be tested to ensure that they will operate properly. Such testing may occur at the point when fabrication of the semiconductor wafer complete and/or after the die has been packaged. A variety of tests have been developed for use during either one of these stages of manufacturing. Most of the tests are administered through a xe2x80x9cprobe cardxe2x80x9d connected to an automated machine. The probe card is a test fixture that makes direct contact with the integrated circuit being tested (also known in this context as the xe2x80x9cdevice under testxe2x80x9d or xe2x80x9cDUTxe2x80x9d). In one form, the probe card includes an electrical interface that is compatible with the DUT. The automated machine controlling the probe card generally includes a computer that has various stored test information developed by the design or test engineers specifically for the DUT. The classes of tests carried out may include functional tests, such as diagnostic tests and stress tests, for ensuring that the functionality of the integrated circuit is complete, and structural tests, such as built-in self-tests (BISTs) and scan-based tests, for ensuring that no structural faults exist in the logic of the DUT.
One of the considerations to selecting the type(s) of test to employ for an integrated circuit is the amount of time each test requires. Because integrated circuits are often part of a mass production process, in which tens of thousands or even millions of units may be produced, even relatively short tests can, in the aggregate, result in significant processing delays. Moreover, post-fabrication tests typically require expensive, specialized test equipment, which can run in the tens of thousands or millions of dollars per test machine. Because integrated circuits increasingly include millions or tens of millions of gates, conventional testing techniques are fast becoming either too time-consuming or ineffective at fully testing integrated circuits. For the same reason, the cost of testing is rapidly becoming the most expensive part of manufacturing an integrated circuit.
A drawback with conventional test procedures is that large amounts of data, in the form of test patterns, often need to be transferred between the tester and the internal circuitry of the integrated circuit, via the probe card connected to the integrated circuit. With potentially millions of gates to be tested on a single integrated circuit, the test patterns can be lengthy. Using the normal interface circuitry of the integrated circuit to load the test patterns and read out the results can take a relatively long amount of time. At-speed stress tests, which typically test system-level functionality at the operational performance limits of the integrated circuit, can be particularly difficult to implement, due to bandwidth constraints between the tester and the integrated circuit device under test.
Some attempts have been made to increase the speed of testing by using a higher speed tester (e.g., one with a speed of 200 MHz, as opposed to the more typical 25 MHz). However, high-speed testers can be inordinately expensive. Also, at such high speeds, the length of the wires connecting the tester to the integrated circuit (via the probe card) can become a significant speed-limiting factor, due to impedances that are in part frequency related. Therefore, very short wires are needed to run a high-speed test, which places design constraints on the test equipment and makes the automated operation of the test equipment potentially more burdensome and expensive.
Another suggested solution has been to include additional test I/O pins on the devices being tested. The problem with this approach is that any improvement is at best linear, and therefore is relatively insignificant in comparison to the increase in the density of gates to be tested for an integrated circuit. Multiple scan test strings might be input into the DUT using the additional test I/O pins, but again the improvement in performance has a low ceiling because of the limited real estate for additional pins. Furthermore, by including additional test pins, the cost for chip packaging increases.
Along the same lines, using signal I/O pins for test has also been suggested to more quickly transfer the test inputs into the DUT. To do this, test and usage I/O are multiplexed for some portion of the set of signal I/O pins. This option, however, incurs performance overhead. Moreover, because the real estate for I/O pins is limited, this alternative provides too limited an advantage.
One of the new developments in circuit designs is the advent of so-called virtual component blocks, which, from a general standpoint, are pre-designed and pre-hardened (or semi-hardened) circuit designs in software form (for example, in GDSII format), which can be readily re-used or recycled in different, larger circuit designs. An advantage of virtual component (or VC) blocks is that they reduce the time to design an overall circuit, and thereby increase the speed to market. Virtual component blocks can also be verified from a logical and functional standpoint, also saving time in the verification portion of the design process.
While virtual component blocks have been found to be convenient from a design perspective, when incorporated in a larger circuit design and fabricated on silicon, they are still subject to fail either due to flaws in the manufacturing process, or due to problems arising from attempted integration into the larger circuit design. Therefore, as with any other type of integrated circuit, integrated circuits based in part on virtual component blocks generally need to be tested and verified at the manufacturing stage to ensure proper functioning. Consequently, according to conventional electronic design automation processes, new tests (whether functional, diagnostic or stress tests) need to be written for each new integrated circuit design incorporating a virtual component block, just as with any other type of new integrated circuit design. These tests can be as time consuming and expensive to design as they are to execute during manufacturing, as mentioned above.
Accordingly, it would be advantageous to provide an improved means for testing integrated circuits, including designing tests, executing tests, and test systems and components at the point of fabrication and/or packaging. It would further be advantageous to provide improved means for testing of integrated circuits developed from pre-defined or pre-hardened virtual component blocks.
The present invention provides, in one aspect, systems and methods for testing integrated circuits.
In a second separate aspect, the present invention is a method of testing an integrated circuit that includes component blocks of random logic in a manufacturing environment. The method preferably includes the steps of performing built-in self tests, at least in part to test memory and data paths of the integrated circuit; performing diagnostics tests, at least in part to test the component blocks of random logic individually; performing stress tests using test vectors, at least in part to test the component blocks of random logic collectively; and performing scan-based tests of the integrated circuit, at least in part to test for structural faults in the integrated circuit.
In a third separate aspect, the present invention is a system for testing an integrated circuit including a memory for storing signatures for initiating built-in self tests, inputs for diagnostic tests, test vectors for stress tests, and scan patterns for scan-based tests. The system preferably further includes a processor for initiating and evaluating performance of the integrated circuit on the built-in self-tests, the diagnostic tests, the stress tests and the scan-based tests.
In a fourth separate aspect, the present invention is a computer-readable medium storing a sequence of instructions for testing a manufactured integrated circuit. The integrated circuit preferably includes a memory, component blocks of random logic and data paths. The sequence of instructions is for performing a set of acts including (a) performing built-in self tests, at least in part to test the memory and datapaths of the integrated circuit; (b) performing diagnostics tests at least in part to test the component blocks of random logic individually; (c) performing stress tests using test vectors at least in part to test the component blocks of random logic collectively; and (d) performing scan-based tests of the integrated circuit at least in part to test for structural faults in the integrated circuit.
In a fifth separate aspect, the present invention is a probe card for testing a device-under-test. The probe card preferably includes a device-under-test interface, a tester interface, and a memory for storing test inputs for the device-under-test. The probe card preferably further includes a data translator connected between the memory and the tester interface for formatting test data communicated between the memory and the tester interface.
In a sixth separate aspect, the present invention is a probe card for testing a device-under-test that preferably includes a device-under-test interface, a tester interface, and an analog signal generator connected between the tester interface and the device-under-test interface. The analog signal generator is preferably configured to receive digital signals representative of analog tests from the tester interface, generate an analog signal based on the digital signals, and transmit the analog signal to the device-under-test interface. The probe card preferably further includes a data translator electrically connected between the device-under-test interface and the tester interface for formatting test data communicated between the device-under-test interface and the tester interface.
In a seventh separate aspect, the present invention is a probe card for testing a device-under-test that preferably includes a device-under-test interface, a tester interface, a fold-back circuit connecting at least two pins of the device-under-test, and a data translator electrically connected between the device-under-test interface and the tester interface. Preferably, the data translator formats test data communicated between the device-under-test interface and the tester interface.
In an eighth separate aspect, the present invention is an integrated circuit that includes circuit component blocks connected via a bus, and I/O pins having corresponding leads connected to the bus. The I/O pins preferably provide a capability for communication external to the integrated circuit. The integrated circuit preferably further includes a fold-back circuit for redirecting a signal transmitted on one of the leads to one of the pins, and fold-back logic for enabling and disabling the fold-back circuit.
In a ninth separate aspect, the present invention is a computer-readable medium storing a sequence of instructions for specifying an integrated circuit. The sequence of instructions is for performing a set of acts including specifying circuit component blocks interconnected via a bus, and specifying I/O pins having leads connected to the bus. The I/O pins preferably provide for a capability for communication external to the integrated circuit. The set of acts preferably further include specifying a fold-back circuit for redirecting a signal transmitted on one of the leads to one of the pins, and specifying fold-back logic for enabling and disabling the fold-back circuit.
In a tenth separate aspect, the present invention is a test station for testing a device-under-test. The test station preferably includes the device-under-test, where the device-under-test includes memory and test logic to lock at least a portion of the memory during a test of the device-under-test. The test station preferably further includes a tester, where the tester is electrically connected to the device-under-test, and is for transmitting digital signals to lock the at least a portion of the memory. The test station preferably further includes a probe card electrically connected to the device-under-test and the tester, where the probe card includes a clock generator for transmitting clock signals to the device-under-test and a data translator electrically connected between the chip interface and the tester interface. Preferably, the data translator formats test data communicated between the chip interface and the tester interface.
In an eleventh separate aspect, the present invention is a method of generating test vectors for testing an integrated circuit at a manufacturing test bench. The method preferably includes steps of obtaining functional level test vectors, converting the test vectors into a series of message blocks, applying an interface protocol to the series of message blocks to generate test vector data, and applying an interface protocol for a device under-test to the test vector data.
In a twelfth separate aspect, the present invention is a system for generating test vectors for testing an integrated circuit at a manufacturing test bench. The system preferably includes a memory for storing functional level test vectors, and a processor connected to the memory for translating the test vectors into message blocks, for applying an interface protocol to the message blocks to generate test vector data, and for applying an interface protocol for a device under test to the test vector data.
In a thirteenth separate aspect, the present invention is a computer-readable medium storing a sequence of instructions for generating test vectors for testing an integrated circuit at a manufacturing test bench. The sequence of instructions is for performing a set of acts including (a) specifying functional level test vectors; (b) translating the test vectors into message blocks; (c) applying an interface protocol to the message blocks to generate test vector data; and (d) applying an interface protocol for the integrated circuit to the test vector data.
In a fourteenth separate aspect, the present invention is a method of generating diagnostic tests for testing an integrated circuit at a manufacturing test bench. The method preferably includes steps of obtaining functional level diagnostic tests for virtual component blocks of an integrated circuit design, translating the diagnostic tests into timing accurate diagnostic tests, converting the timing accurate diagnostic tests into memory load instructions, and applying an interface protocol for a device under test to the memory load instructions.
In a fifteenth separate aspect, the present invention is a computer-readable medium storing a sequence of instructions for specifying and testing a manufactured integrated circuit. The sequence of instructions is for performing a set of acts including (a) specifying virtual component blocks; (b) specifying interconnections between the virtual component blocks; (c) specifying sets of diagnostic tests for testing manufactured forms of the virtual component blocks, where each set of diagnostic tests corresponds to one of the virtual component blocks; and (d) specifying a set of test vectors for testing the manufactured integrated circuit.
In a sixteenth separate aspect, the present invention is a computer-readable medium storing a sequence of instructions for generating and/or translating tests vectors for testing an integrated circuit at a manufacturing test bench. The sequence of instructions is for performing a set of acts including (a) specifying functional level test vectors for testing a functional specification of the integrated circuit; (b) translating the test vectors into message blocks; (c) applying an interface protocol to the message blocks to generate test vector data; (d) applying an interface protocol of the integrated circuit to the test vector data.
In a seventeenth separate aspect, the present invention is a method of manufacturing a computer readable medium storing a design for an integrated circuit and a collection of test inputs for manufacturing and functionally testing a manufactured form of the integrated circuit. The method preferably includes the steps of (a) designing virtual component blocks to be used in the design of the integrated circuit, (b) designing a diagnostic test specific to each virtual component block, (c) determining the design for the integrated circuit comprising the virtual component blocks, (d) obtaining high level test vectors for the integrated circuit, (e) verifying the integrated circuit using the test vectors and the diagnostic tests, (f) augmenting the diagnostic tests and the test vectors for a manufacturing environment, and (g) packaging the design for the integrated circuit with the augmented test vectors.